BURIED WORDLINE PDF

And they are in volume production, we have also found them in a point and shoot camera. Therefore, in the above structure, the semiconductor device having a height corresponding to the protruded portion of the metal gate electrode 20 is formed. Example embodiments relate to a semiconductor device having a buried gate electrode and a method of fabricating the same. The gate electrode layer may be formed of polysilicon.

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Usually, the technology node for DRAM is defined as the half-wordline pitch. However, the unit cell of this new device is 40 percent smaller than that of the nm node device. Hynix 44 nm and Hynix 31 nm both have the same WL pitch 88 nm , which by conventional definition implies that the technology node is 44 nm. Hynix nm device uses a buried wordline line integration scheme and has a smaller unit cell than Hynix 44 nm.

Pitch defines node Another common definition for technology node is the minimum lithographically implemented feature size. Half of the WL pitch represents the minimum feature size. Irrespective of what parameter the manufacturer has taken as the minimum feature size, one parameter is common: every new technology node has a smaller SDRAM cell area than the previous generation.

It is the only memory device that uses half-STI pitch to define the technology node while utilizing a new cell layout. Hynix was the only manufacturer still using 8F2 layout for subnm nodes. The 8F2 layout has two major advantages: 1. The noise immunity is higher and the process complexity is lower due to larger cell size compared to the 6F2 layout. Conversely the 6F2 scheme provides a significant 25 percent cell area reduction with the same design rule.

Hynix continued using 8F2 layout until the introduction of this device. Saddle-fin transistor At the nm node, Hynix used a saddle-fin transistor as an access device but maintained the old layout of 8F2. The saddle-fin transistor was designed to decrease storage node write time as well as improve short channel effects with the addition of a partial triple-gate structure. However, it has become increasingly difficult to shrink the cell size using the 8F2 layout. As a result, Hynix eventually adopted the 6F2 layout while also implementing the bWL concept.

In the bWL cell, the transistor gates are merged with the metal WL running below the silicon surface level, thus enabling a simple cell structure. Due to a less complex structure, the BL-to-WL capacitive coupling is strongly reduced, resulting in a higher read margin and, subsequently, lower power consumption.

Hynix has kept the same WL pitch as that of its previous generation but has reduced the STI spacing by making the active area slanted by 19 degrees from the BL direction as shown in the figure below. The slanted active areas are not continuous but form islands separated by STI. Active areas of Hynix nm device are slanted and the bitline makes a 19 degree angle with the active area. This configuration helps to reduce the cell area and to keep straight bitlines.

The rest of the Hynix nm device process is similar to its previous nm node technology. Even though the capacitor module and the peripheral transistors are identical to the previous generation, the nm-class Hynix SDRAM is still a major step for the company and its viability. This is not cost effective in terms of production.

Smaller cell area Moreover, Hynix has also switched over to a 6F2 layout from a 8F2 layout, which it used for at least five generations. The figure below shows the square root of DRAM cell area versus technology node. That is because the other two manufacturers chose to utilize the 6F2 layout.

This same figure also suggests that for each manufacturer the square root of its SDRAM cell area decreases linearly as a function of technology node. It makes a lot of sense to consider the SDRAM unit cell area as the main parameter to define a technology node. All four manufacturers use different novel process innovations to shrink their respective SDRAM cell area. From this analysis, it is interesting to see the novel approach each DRAM manufacturer takes in developing towards their next process shrink as the highly volatile and competitive DRAM market is taken into consideration with each design.

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