UCC3802 PDF

A Typical Starting Supply Current? A Typical Operating Supply Current? Operation to 1MHz? Internal Soft Start?

Author:Voodootilar Togul
Country:Hungary
Language:English (Spanish)
Genre:Video
Published (Last):21 March 2012
Pages:460
PDF File Size:1.22 Mb
ePub File Size:9.7 Mb
ISBN:880-4-51065-602-4
Downloads:89572
Price:Free* [*Free Regsitration Required]
Uploader:Mazukus



The control for many of these switchmode supplies was revolutionized with two significant introductions; an advance technique known as current mode control, and a novel PWM solution, the UC controller. This IC contained several innovative features for general purpose current mode controlled applications. Included were high speed circuitry, undervoltage lockout, an op-amp type error amplifier, fast overcurrrent protection, a precision reference and a high current totem-pole output.

The popular UC control circuit architecture has been recently improved upon to deliver even higher levels of protection and performance. Advanced circuitry such as leading edge blanking of the current sense signal, soft-start and full cycle restart have been built-in to minimize external parts count.

Additionally, these integrated circuits have been developed on a BiCMOS wafer fabrication process geared to virtually eliminate supply power and propagation delays in comparison to the bipolar UC devices. This application note will highlight the features incoporated into this new generation of PWM controllers in addition to realizeable enhancements in typical applications.

Low start-up current B. Undervoltage lockout C. Low operating current D. Internal soft start E. Leading Edge Blanking G. Self regulating Vcc supply H. Full cycle restart after fault I. Clamped gate drive amplitude J. Reduced propagation delays K. There are a few important differences however which may require minor modifications to existing applications. Maximum supply voltage from a low impedance source: 12V versus 30V 2. Undervoltage lockout thresholds 3.

Start-up current 4. Operating current 5. Oscillator timing component values 6. Reference voltage UCC and 05 7. Vcc supply self clamping zener voltage 8. Internal soft start 9.

Internal full cycle restart Clamped gate drive voltage Current loop gain A series resistor from Vcc to the input supply source is required with inputs above 12 volts to limit the shunt regulator current as shown in figure 2. A maximum of 10 milliamps can be shunted to ground by the internal regulator. The supply voltage is MOSFET gate level compatible and needs no external zener diode or regulator protection with a current limited input supply.

The UVLO start-up threshold is 1. It is important to bypass the ICs supply Vcc and reference voltage Vref pins with a 0. The capacitors should be located as close to the actual pin connections as possible for optimal noise filtering.

A second, larger filter capacitor may also be required in offline applications to hold the supply voltage Vcc above the UVLO turn-off threshold during start-up. Basically, the thresholds are optimized for two groups of applications; off-line power supplies and DC-DC converters. Once crossing the turnon threshold the IC supply current increases typically to about microamps, over an order of magnitude lower than bipolar counterparts. Figure 3. Powering the UCC An active low, self biasing totem pole output during UVLO design is also incorporated for enhanced power switch protection.

Power to this circuit is supplied by the externally rising gate voltage, so full protection is available regardless of the ICs supply voltage during undervoltage lockout. The noninverting input to the error amplifier is tied to one-half of the PWMs reference voltage, Vref.

Note that this input is 2. Figure 5: Output voltage vs. This change was necessary to facilitate operation with input supply voltages below five volts.

Many of the reference voltage specifications are similar to the UC devices although the test conditions have been changed, indicative of lower current PWM applications.

It does still utilize a resistor to the reference voltage and capacitor to ground to program the oscillator frequency up to 1 MHz. Timing component values will need to be changed since a much lower charging current is desirable for low power operation. Several characteristics of the oscillator have been optimized for high speed, noise immune operation.

The oscillator peak to peak amplitude has been increased to 2. The lower oscillator threshold has been dropped to approximately 0. Whenever Vcc is below approximately 4. The relationship between Vcc and Vref during this excursion is shown in Figure 7. Practical applications can utilize these new ICs to a 1 MHz switching frequency. A brief positive pulse is applied across the 50? Typically, a one volt amplitude pulse of nanoseconds width is sufficient for most applications.

Note that the IC will internally pull low at this node once the upper oscillator threshold is crossed. This ohm impedance to ground remains active until the pin is lowered to approximately 0. External synchronization circuits should accommodate these conditions.

Figure 8: Oscillator equivalent circuit. Discharge current of the timing capacitor has been increased to nearly 20 milliamps peak as opposed to roughly 8mA. As shown, this can be represented by approximately ohms in series with the discharge switch to ground. This is primarily due to the higher ratio of timing capacitor discharge to charge current which can exceed onehundred to one in a typical BiCMOS application.

Attempts to program the oscillator maximum duty cycle much below the specified range by adjusting the timing component values of Rt and Ct should be avoided.

There are two reasons to refrain from this design practice. First, the ICs high discharge current would necessitate higher charging currents than necessary for programming, Figure Oscillator frequency vs. RT for several CT. Adding this discharge control resistor has several impacts on the oscillator programming. First, it introduces a DC offset to the capacitor during the discharge — but not the charging portion of the timing cycle, thus lowering the usable peak-to-peak timing capacitor amplitude.

Because of the reduced peak-to-peak amplitude, the exact value of Ct may need to be adjusted from UC type designs to obtain the correct initial oscillator frequency. One alternative is keep the same value timing capacitor and adjust both the timing and discharge resistor values since these are readily available in finer numerical increments.

Figure Synchronizing the oscillator. Secondly, a low value timing resistor will prevent the capacitor from discharging to the lower threshold and initiating the next switching cycle. Figure Circuit to produce controlled maximum duty cycle. It is used to insure that even at maximum duty cycle, there is enough time to reset the magnetic circuit elements, and prevent saturation.

Larger capacitance values extend the deadtime whereas smaller values will result in higher maximum duty cycles for the same operating frequency. A curve for deadtime versus timing capacitor values is provided in figure The deadtime increases with the discharge resistor value to about Ohms as indicated from the curve. Higher resistances should be avoided as they can decrease the deadtime and reduce the oscillator peak-to-peak amplitude. Sinking too much current 1 mA by reducing Rt will Figure Maximum duty cycle vs.

This internal feature has been incorporated to eliminate the need for an external resistor-capacitor filter network to sup- Figure Current sense filter required with older PWM ICs. Note that the ns leading edge blanking is also applied to the cycle-by-cycle current limiting function in addition to the overcurrent fault comparator.

UA this network is used to guarantee that zero duty cycle can be reached. Note that the nanosecond leading edge blanking pulse is applied to this current limiting circuitry. The blanking overrides the current limit comparator output to prevent the leading edge switch noise from triggering a current limit function. Propagation delay from the current limit comparator to the output is typically 70 nanoseconds. This high speed path minimizes power semiconductor dissipation during an overload by abbreviating the on time.

Figure Current sense waveforms with leading edge blanking. Resistors RA and RB bias the actual current sense resistor voltage up, allowing a small current sense amplitude to be used. This circuitry provides current limiting protection with lower power loss current sensing. This will occur when the error amplifier output voltage minus a diode drop and divided by 1.

However, the amplifier output voltage must also be higher than a diode forward voltage drop of about 0. It is only during these conditions that a minimum output pulse width equal to the blanking duration can be obtained. Note that the PWM comparator has two inputs; one is from the current sense input. The other PWM input is the error amplifier output which has a diode and two resistors in series to ground.

The diode in Figure Biasing Isense for lower current sense voltage. Figure Zero duty cycle is achievable by forcing the error amplifier output below the zero duty cycle threshold of one diode voltage drop. The example shown uses a millivolt full scale signal at the current sense resistor.

ITEXTSHARP ADD JAVASCRIPT TO EXISTING PDF

Semiconductor UCC3802 de circuito integrado de componente electrónico

.

SHIBUMI TREVANIAN PDF

.

KAKO PREZIVETI SOPSTVENI HOROSKOP PDF

.

AN INTRODUCTION TO HIGH VOLTAGE ENGINEERING BY SUBIR RAY PDF

.

Related Articles